Effort Delay, Logical Effort, Electrical Effort, Parasitic Delay | Know - How

This video on "Know-How" series helps you to understand the linear delay model of basic CMOS gates. The delay model includes the analysis of two major components namely, effort delay and parasitic delay. The effort delay is product of logical effort and electrical effort. The logical effort and parasitic delay of CMOS Inverter, CMOS NAND2 & CMOS NOR2 gates are calculated. To have better knowledge on unskewed CMOS design, watch the video link shared below:    • Transistor Sizing - Catalog of Skewed Gate...   TimeCodes Introduction to Linear Delay Model: (0:00) Unskewed - CMOS Inverter: (01:53) Unskewed - CMOS NAND2 Gate: (04:35) Unskewed - CMOS NOR2 Gate: (08:02) Logical Effort of Common Gates: (10:04) Parasitic Delay of Common Gates: (10:37)