Lecture 17: Optimal number of stages for minimum delay, reducing logical effort

This lecture covers the following. Recap of logical effort based linear delay model and delay optimizations Optimal number of stages for minimal delay Techniques to reduce delay of an individual gate Input reordering Asymmetric gates Skewed gates Pseudo NMOS logic gates EE619A: VLSI system design (2023) Instructor: Chithra ( https://home.iitk.ac.in/~chithra ) MVLSI, EE, IIT Kanpur For more lectures on other topics from our lab, you may visit https://www.iitk.ac.in/sscd/Teaching....