Delay in Multistage Logic Network | Know - How
This video on "Know-How" series helps you to estimate the linear delay of a multistage logic network. An example problem has been solved to calculate the overall delay of the multistage logic network. Also, the transistor sizing is obtained based on the overall Fan-out of the logic network. To understand the basic linear delay model for basic CMOS gates watch the video link shared below: • Effort Delay, Logical Effort, Electrical E... TimeCodes Delay in a Logic Gate: (0:00) Multistage Logic Network - Problem: (01:22) Delay in a Multistage Logic Network: (02:30) Path Electrical & Logical Effort: (04:15) Overall Delay & Parasitic Delay: (05:58) Overall Fan - Out: (08:50) Transistor Sizing: (10:43) Final circuit of Multistage Logic Network: (14:22)
