Instruction Set Architecture (ISA) in a Real CPU

In this video, we take Instruction Set Architecture out of the textbook and wire it directly into a working 16-bit CPU. Using the RTM-16 as a real example, we explore: • how opcode bits are allocated • how register fields constrain connectivity • how 2-operand vs 3-operand formats affect hardware • how addressing modes shape the datapath ISA is not just an abstract design choice. Every bit decision has hardware consequences. This is where theory becomes engineering: ISA design → instruction encoding → datapath structure → real hardware constraints. Chapters 00:00 The Machine in Action 00:20 Why This Matters (Not Just Theory) 01:05 The Bit Structure (6+2+4+4) 07:29 ISA Wired Into Real Hardware 14:17 Summary If you’d like to follow the full structured build — from logic gates to FPU to compiler — you can support the project here:   / rossmcgowanmaths   Topics covered: instruction set architecture (ISA) instruction format design opcode allocation 2-operand vs 3-operand tradeoffs register encoding constraints addressing modes in hardware datapath implications 16-bit CPU architecture (RTM-16)